Dynamic Random Access Memory (DRAM) has been considered as an alternative to Static Random Access Memory (SRAM) in embedded memories operating at low power supply conditions. This is because DRAM has several advantages over SRAM as it requires lesser chip area and it does not experience memory contention and read or write instabilities which limit the minimum power supply voltage (Vmin) at which the DRAM can operate correctly.
However, memory charge retention is becoming increasingly important in embedded DRAM with the improvement of transistor technology. The feature size of transistors is shrinking and the scaling effect of the transistors reduces the capacitance of the memory cell storage node of the DRAM cell. The reduced capacitance, coupled with the higher leakage of the transistor in the DRAM cell as transistor technology improves, affects the memory charge retention of the DRAM cell.
When memory charge retention of the DRAM cell is reduced, more refresh cycles are needed to maintain the charge in the memory cell storage node. Refresh cycles are considered wasted time that impact performance and DRAM cells are recharged more often as transistor technology improves. The prior art typically attempts to solve the memory charge retention problem of DRAM cells by increasing the voltage of the memory cell storage nodes of the DRAM cells or by optimizing the fabrication process to reduce leakage and developing novel devices and capacitors, rather than relying on circuit techniques.
FIG. 1 shows a DRAM cell 100 where the gate node of the transistor 120 is connected to a word line 110 and the drain node of the transistor 120 is connected to a bit line 150. Element 140 is a storage capacitor in a 1 Transistor (1T) DRAM cell or the N-channel Metal Oxide Semiconductor (NMOS) gate in a gain cell. The memory cell storage node 130 of the DRAM cell 100 is connected to the storage capacitor or NMOS gate 140 that stores the charge or data. To minimize the memory charge retention problem in the DRAM cell 100, the commonly used solution is to increase the voltage of the memory cell storage node 130 by increasing the voltage of the word line 110. However, this solution may result in reliability issues as higher voltage is used. One circuit technique 200, as shown in FIG. 2, proposes a gated diode 260 to be added to a three transistors (3T) DRAM cell that acts as a storage device and amplifier.